The present invention generally relates to silicon-on-insulator (SOI) technology, and more particularly to an SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and a method of fabricating the same.
In the semiconductor manufacturing industry, there has been a great deal of attention paid to reducing parasitic capacitance and resistance to increase the operating speed of semiconductor integrated circuits. SOI MOSFETs have been demonstrated to be superior to bulk silicon MOSFETs in terms of low power, high speed very large scale integration (VLSI) applications because of their inherent merits such as less junction capacitance and better device isolation. In addition, there are many advantages in SOI devices such as better immunity to soft errors, reduction in dynamic power, improvement in latch-up resistance even with increased packing density. Despite the above outstanding features of SOI devices, Sol integrated circuits have suffered some lack of commercial success due to technical problems in material processing and device design.
FIG. 1 depicts a typical structure of an SOI MOSFET according to the prior art. The SOI MOSFET includes a gate electrode 20, a gate dielectric 21, a source 23 and drain 24 on insulating layer 15. A backside surface of the insulating layer 15 is in contact with a supporting substrate 10.
Since the body region 30 of the SOI MOSFET is isolated by the insulating layer 15, it is electrically isolated and therefore its voltage varies with the voltage applied to either source region 23, drain region 24, or gate electrode 20.
The voltage fluctuation of the body region 30 in SOI MOSFET, commonly referred to as the floating body effect (FBE), causes detrimental effects for the proper operation of SOI devices. The most common of these detrimental effects are the kink effect and the bipolar effect. With the channel region of the device partially depleted and a high drain voltage applied, the electric field created in the device causes impact ionization near the drain region 24.
Accordingly, in the event that the SOI MOSFET is an SOI N-MOSFET, the generated holes are injected into the body thereby creating a positively charged body. The first consequence of this positive charge accumulated in the body 30 is the increase of the body potential resulting in a decrease of the threshold voltage (VT) of the SOI MOSFET. Since the decrease of the threshold voltage raises the drain current, the variation of threshold voltage shows up as kinks in the output characteristics of the SOI MOSFETs.
Another consequence of the voltage increase is the eventual turn-on of the lateral bipolar structure since the MOSFET includes a lateral bipolar transistor, i.e., the n-p-n construction 23, 30, and 24. As the body 30 of the MOSFET becomes positively biased, the source-body (23-30) junction, corresponding to emitter-base junction of the lateral n-p-n construction, becomes forward biased, and electrons are injected from the source 23 into the body region 30. The injected electrons reaching the drain depletion region add to the drain current. Consequently, the drain current is dominantly controlled by the parasitic bipolar transistor rather than by the channel current under the gate electrode control. This effect is referred to as the parasitic xe2x80x9cbipolarxe2x80x9d effect. The parasitic bipolar action of the SOI MOSFET induces a xe2x80x9cdynamic leakage currentxe2x80x9d(DLC) especially in a switching circuit.
In a MUX (multiplexer) circuit as depicted in FIG. 2A, if the applied voltages at nodes A and B are high, then the output node C will be high. If the gate voltage of the node A is switched to a low voltage, then the output node C should be kept to a high voltage. However, in a state that the nodes A and C keep a low voltage and a high voltage, respectively, if the voltage at node B is switched to a low voltage for some reason, the output voltage at node C drops instantaneously by the dynamic leakage mechanism due to the parasitic bipolar effect. FIG. 2B illustrates the instantaneous drop of the output voltage at node C in the multiplexer circuit according to the prior art. Here, the x-axis represents time (t) and the y-axis represents voltage of the node C.
In order to remedy those detrimental effects due to the floating body effect observed in SOI MOSFETs, several technical approaches have been proposed. For instance, F. Assaderaghi et al. proposed a technique for reducing the floating body effect in their technical paper entitled, xe2x80x9cA dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation,xe2x80x9d published in IEEE Electron Device Lett., pp.510-512, Vol.15, No. 12, 1994. F. Assaderaghi et al. tried to eliminate the floating body effect by tying the floating body to the gate of the SOI MOSFET. However, since the dynamic leakage current cannot be avoided between source and drain when the gate voltage is high while keeping source and drain low, they pointed out that their approach is only applicable to the low voltage operation.
As another approach to resolve the floating body problem in SOI devices, J. W. Sleight et al. proposed a Schottky body contact technology in a technical paper entitled, xe2x80x9cDC and transient characterization of a compact Schottky body contact technology for SOI transistors,xe2x80x9d published in IEEE Transactions on Electron Devices, pp. 1451-1456, Vol. 46, No. 7, July 1999. This technical paper provides a self-aligned Schottky diode method for body contacting partially depleted SOI transistors. In their paper, Schottky diodes are placed at source/drain terminals, allowing the floating body to be tied to the source/drain region.
FIGS.3A and 3B are schematic layout diagrams for implementing body contact tied to source/drain and gate, respectively, according to the prior art. Referring to FIG. 3A, n+source 23 is tied to the body 30 through p+regions 31. Referring to FIG. 3B illustrating the gate-body contact in accordance with the first prior art paper mentioned above, the body 30 is electrically connected to the gate electrode 20 through electrical contact 33.
However, it should be noted that the body contacting schemes either to source or gate disclosed in the prior art have fundamental limitations in their application to commercial SOI integrated circuits. Namely, since only the weak parts vulnerable to the dynamic leakage current out of the whole circuit are manually cured by contacting the floating body according to the prior art, it is difficult to resolve the inherent floating body problem in SOI integrated circuits.
For instance, only 50 to 100 thousand transistors are usually body-contacted to remedy the floating body effect out of 1.5 million transistors comprising the 64-bit microprocessor fabricated on SOI substrate.
In view of these problems, there is need for a method and structure for fundamentally eliminating the floating body effect in SOI semiconductor integrated circuits; which is not subject to these limitations.
Accordingly, it is an object of the present invention to provide a technique to eliminate the floating body effect in SOI integrated circuits. It is another object of the present invention to provide a technique to resolve the kink effect in SOI integrated circuits.
It is another object of the present invention to provide a technique to eliminate the parasitic bipolar effect and consequently the dynamic leakage current in SOI integrated circuits.
It is another object of the present invention to provide a technique to eliminate the floating body effect, which is applicable to commercial SOI products.
It is another object of the present invention to provide a complete solution to eliminate the floating body effect while keeping the conventional layout compatibility.
Accordingly, the invention is directed to a SOI semiconductor integrated circuit and a method of making the same. The SOI integrated circuit of the invention is formed on an SOI substrate including a supporting substrate, a buried insulating layer on the supporting substrate and a semiconductor layer of a first conductivity type on the buried insulating layer. The SOI integrated circuit of the invention includes at least one isolated transistor active region including a predetermined region of the semiconductor layer. A body line of the first conductivity type is disposed at one side of the transistor active region, the body line including a portion of the semiconductor layer. An isolation layer surrounds sidewalls of the transistor active region and the body line, the isolation layer being in contact with the buried insulating layer. A body extension of the first conductivity type extends from a predetermined sidewall of the transistor active region and is connected to the body line, the body extension being thinner than the transistor active region. A body insulating layer is formed on the body extension. An insulated gate pattern crosses over the transistor active region, the insulated gate pattern overlapping with the body insulating layer.
In accordance with the present invention, provided are SOI semiconductor integrated circuits having a body extension which connects a body region of an SOI MOSFET to a body line tied to the power line or the ground line and methods of fabricating the SOI semiconductor integrated circuits.
An SOI integrated circuit according to an embodiment of the present invention comprises at least one isolated SOI MOSFET surrounded by insulator, a body line disposed at one side of the SOI MOSFET and a body extension which electrically connects a sidewall of a body region of the SOI MOSFET to the body line. Therefore, a plurality of SOI MOSFETs may be disposed at one side of the body line. In addition, the plurality of SOI MOSFETs may be disposed at both sides of the body line.
In one embodiment, the first conductivity type is P type. In an alternative embodiment, the first conductivity type is N type. In one embodiment, the SOI integrated circuit includes a metal silicide layer formed on the body line.
In one embodiment, a gate insulating layer is interposed between the insulated gate pattern and the transistor active region and one end of the insulated gate pattern is overlapped with the body insulating layer. The body insulating layer is thicker than the gate insulating layer. Thus, it can prevent an inversion channel from being formed at the body extension regardless of the voltage applied to the insulated gate pattern. As a result, it becomes possible to implement an improved SOI MOSFET without floating bodies in the whole SOI integrated circuits.
An SOI integrated circuit according to another embodiment of the present invention is formed on an SOI substrate including a supporting substrate, a buried insulating layer on the supporting substrate and a semiconductor layer of a first conductivity type on the buried insulating layer. The SOI integrated circuit of the invention includes at least one transistor active region and at least one body contact active region spaced apart from the transistor active region. The transistor active region and the body contact active region are composed of a portion of the semiconductor layer. The buried insulating layer, which is located between the transistor active region and the body contact active region, is covered with a semiconductor residue layer. The semiconductor residue layer is thinner than the transistor active region and the body contact active region. As a result, a partial trench region exists between the transistor active region and the body contact active region. The partial trench region is filled with a partial trench isolation layer. A full trench isolation layer is interposed between the transistor active region and the partial trench isolation layer. The full trench isolation layer is in contact with the buried insulating layer. Thus, the full trench isolation layer surrounds sidewall of the transistor active region. A body extension is extended from a portion of the sidewall of the semiconductor residue layer toward the transistor active region. The body extension connects the transistor active region to the semiconductor residue layer and is covered with the partial trench isolation layer. An insulated gate pattern crosses over the transistor active region. The body extension is overlapped with at least one end of the insulated gate pattern.
The present invention further comprises source/drain regions formed at the transistor active region, which is located at both side of the insulated gate pattern. Preferably, the source/drain regions is in contact with the buried insulating layer. Thus, the source/drain regions are surrounded the full trench isolation layer and the buried insulating layer.
The invention is also directed to a method of making a SOI semiconductor integrated circuit on an SOI substrate including a supporting substrate, a buried insulating layer on the supporting substrate and a semiconductor layer of a first conductivity type on the buried insulating layer. In accordance with the method, a predetermined region of the semiconductor layer is etched to form a trench region defining at least one isolated transistor active region and a body line active region at one side of the transistor active region and concurrently leaving a semiconductor residue layer, which is thinner than the semiconductor layer at a bottom of the trench region. The semiconductor residue layer is selectively etched until the buried insulating layer is exposed, thereby forming an isolation region and concurrently leaving a body extension of the first conductivity type connecting the transistor active region to the body line active region. A body insulating layer and an isolation layer are formed on the body extension and the exposed buried insulating layer, respectively. An insulated gate pattern is formed crossing over the transistor active region and overlapping with the body insulating layer. The body line active region is doped with impurities of the first conductivity, type to form a body line.
A method of fabricating the SOI integrated circuit in accordance with the invention includes forming at least one SOI MOSFET at an SOI substrate, forming a body line disposed at one side of the SOI MOSFET and forming a body extension that electrically connects a body region of the SOI MOSFET to the body line. Here, the SOI substrate includes a supporting substrate, a buried insulating layer formed on the supporting substrate and a semiconductor layer formed on the buried insulating layer. Thus, a plurality of SOI MOSFETs may be formed at one side of the body line or at both sides of the bit line.
The method of forming the SOI MOSFET, the body line and the body extension comprises etching a predetermined region of the semiconductor layer to form a trench region defining at least one isolated transistor active region and a body line active region at one side of the transistor active region. The depth of the trench region is smaller than the thickness of the semiconductor layer. Thus, a semiconductor residue layer, which is thinner than the semiconductor layer, exists at the bottom of the trench region. A predetermined region of the semiconductor residue layer is then selectively etched until the buried insulating layer is exposed, thereby leaving a body extension that connects the transistor active region to the body line. Accordingly, an isolation region exposing the buried insulating layer is formed. As a result, the isolation region is deeper than the trench region exposing the body extension.
Subsequently, a body insulating layer and an isolation layer are formed in the trench region exposing the body extension and in the isolation region exposing the buried insulating layer, respectively. An insulated gate pattern crossing over the transistor active region is formed. The gate pattern is formed so that one end of the gate pattern is overlapped with the body insulating layer. Here, a gate insulating layer is formed between the gate pattern and the transistor active region. The body insulating layer is thicker than the gate insulating layer. Thus, even though a predetermined voltage in the range of operating voltage is applied to the gate pattern, it can prevent an inversion channel from being formed at the body extension under the body insulating layer. Impurity ions having the same conductivity type as the semiconductor layer, i.e., a body region of the SOI MOSFET are implanted into the body line active region to form a body line having a low resistivity.
A method of fabricating the SOI integrated circuit in accordance with an embodiment of the invention includes providing an SOI substrate having a supporting substrate, a buried insulating layer and a semiconductor layer which are sequentially stacked. A predetermined region of the semiconductor layer is etched to form a partial trench region defining at least one transistor active region and at least one body contact active region spaced apart from the transistor active region and concurrently leaving a semiconductor residue layer, which is thinner than the semiconductor layer at a bottom of the partial trench region. The semiconductor residue layer is selectively etched until the buried insulating layer is exposed, thereby forming a full trench region surrounding the transistor active region and concurrently leaving a body extension of the first conductivity type connecting the transistor active region to the semiconductor residue layer. A partial trench isolation layer and a full trench isolation layer are formed in the partial trench region and the full trench region, respectively. An insulated gate pattern is formed crossing over the transistor active region and overlapping with the partial trench isolation layer on the body extension.
The present invention further comprises forming source/drain regions of a second conductivity type at both sides of the insulated gate pattern. The source/drain regions are formed to be in contact with the buried insulating layer.